The invention relates to a method of manufacturing a semiconductor heterostructure, comprising manufacturing a donor wafer, comprising providing a first substrate with a first in-plane lattice parameter, providing on the first substrate an at least spatially graded buffer layer having on top in a relaxed state a second in-plane lattice parameter, forming on the graded buffer layer an ungraded layer of a semiconductor material having in relaxed state a third in-plane lattice parameter, forming on the ungraded layer a top layer of a semiconductor material, and manufacturing a handle wafer, comprising providing a second substrate, forming on the second substrate an insulator layer, and bonding the donor wafer with the handle wafer.
Semiconductor heterostructures like this are used, for instance, to transfer the top layer or the top layer and a part of the ungraded layer by means of splitting of the donor wafer onto the handle wafer.
A principal structure of a donor wafer is known from U.S. Pat. No. 5,442,205 disclosing semiconductor heterostructure devices with strained semiconductor layers. The known heterostructure includes a strained epitaxial layer of silicon or germanium which is located over a silicon substrate with a spatially graded GexSi1-x epitaxial layer, which in turn is overlaid by an ungraded Gex0Si1-x0 layer, intervening between the silicon substrate and the strained layer. Such heterostructures can serve, for instance, as a foundation for surface emitting LEDs or MOSFETs. The spatially graded GexSi1-x layer is used to adapt the lattice parameter between the underlying substrate and the deposited relaxed material, while trying to minimize the density of defects. Usually, the ungraded layer of SiGe with constant Ge concentration corresponding to the concentration obtained at the top of the graded layer is provided as a relaxed layer to improve the crystalline quality of the structure.
The structure obtained usually has a surface morphology that is not suitable for further use, in particular for bonding or growing of further layers thereon. US patent application 2003/0215990, which is preoccupied with preventing interdiffusion of dopants in semiconductor heterostructures, proposes a planarization step, in particular a Chemical Mechanical Polishing (CMP) step, before growing any further layer. Here it is the role of CMP to provide a polished smooth surface, which is typically of about 2 Å. Following CMP, the substrate needs to be further treated to prepare the subsequent layer deposition. Such treatments include treating the surface using a HF solution and furthermore a bake or other treatment to remove oxides. This application also proposes epitaxial deposition of further layers such as silicon germanium or strained silicon layers.
It appears, however, that the resulting surface properties for the semiconductor heterostructures are unsuitable when applying the above described prior art processes. Indeed, due to the bake prior to the deposition of the further layers, a roughening of the silicon germanium surface occurs. During the subsequent growth of, e.g., a strained silicon layer, the surface roughness tends to diminish again the final roughness, but nevertheless stays considerably higher than the roughness of the graded GeSi layer surface or of the capping layer, if present, after the CMP process, as the thickness of the strained silicon layer cannot exceed a critical thickness beyond which defects would nucleate within the layer or at the interface of the strained and the underlying layers. Therefore, the overall thickness of the strained silicon layer is too thin, so that no additional CMP can be carried out for flattening out the surface of the strained silicon layer to the desired values. In addition to the thickness aspect allowing a partial improvement of the surface roughness, US patent application 2003/0215990 also proposes to control the temperature at which the layers are grown after planarization, but still only final surface roughness values of the order of 5 Å are achieved at best.
Although, this procedure leads to a decrease of surface roughness of the strained top layer, it does not influence the roughness of the interface between the strained top layer and the underlying SiGe layer. Since even this interface will be the top surface of the finished sSOI product after layer transfer and removal of the remainder of the split SiGe layer, the resulting sSOI structure will still have an increased surface roughness.
Because of the high surface roughness and overall topology of the top layer of the donor wafer, problems such as non-transferred areas, voids, etc. occur during direct wafer bonding of the donor wafer with a handle wafer whether or not an insulator layer is provided on the handle wafer. These problems are in particular critical if the structure is implanted before bonding to be split after bonding as known from the SMART-CUT® process. Although it is, in general, possible to anneal a bonded structure for a certain time at elevated temperatures to reinforce the bonding strength despite of unfortunate surface properties of the bonded wafers, such a heat treatment at high temperature is not recommended for use in the SMART-CUT® process. Here, it is important to have a very good bond before splitting which is performed at about 400 to 500° C. Therefore, the surface condition of a donor wafer has to be nearly perfect before bonding such that the bond is of high quality even after low temperature bonding at about 200° C. A “nearly perfect” surface not only has to be of low roughness but should also have a very planar surface, i.e., a very homogeneous surface topography.
Furthermore, it has been observed that splitting for layer transfer results in less defects when an insulator is provided on the handle substrate. An explanation for this effect can be that the species implanted in the donor wafer may diffuse toward the bonding interface and that this can be prevented by the existence of an insulator layer on the donor to block this diffusion. To absorb these species before they reach the interface and prevent an efficient bonding thus results in a higher quality splitting.
For bonding of the donor wafer, it was therefore necessary to form on the top layer of the donor wafer an insulator layer, e.g. by means of an oxidation step of the top layer or, more preferably, by deposition of an insulator layer because the top layer is generally too thin to accurately be formed by oxidation. Since the formation of an insulator layer on the donor wafer is connected with a thermal treatment of the donor wafer, the thermal load on the donor wafer could exceed a certain thermal budget of the donor wafer causing, for instance, an unintentional diffusion of germanium inside of the donor wafer leading in turn to diffuse interfaces between the layers of the donor wafer.
As deposition tends to form a rough surface, an additional polishing step may be necessary and as a consequence a uniform thickness of the resulting insulator layer is difficult to achieve. Because of deposition and/or polishing of the insulator, thickness non-uniformities of the formed insulator layer can occur. This thickness variance influences the emissivity of the final substrate which affects the temperature distribution on its surface during further processing such as epitaxial deposition on the SOI substrate to provide thicker strained silicon values or devices manufacturing processes.
Furthermore, the bad uniformity and topography of a donor wafer having an oxide deposited thereon complicates bonding of the donor wafer with a handle wafer.
In view of the above, it is apparent that improvements in surface roughness of such materials are needed.